1. Technical Field
This disclosure relates to memory modules and memory systems having the same, and more particularly to memory modules operating at high operating clock frequencies and memory systems having the same.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional memory module. FIG. 1 shows a memory module having eight ×8 dynamic random access memory (DRAM) devices.
Referring to FIG. 1, a command/address bus 12 (CA) is split to be coupled to each of the eight DRAM devices 20-1 to 20-8. Eight read/write data buses 14 (DQ) are respectively coupled to the eight DRAM devices 20-1 to 20-8.
As an operating speed of memory devices increases, it becomes more difficult for the memory devices to share a command/address bus CA and a read/write data bus due to the capacitive loading of input/output (I/O) lines of the memory devices. Conventional synchronous dynamic random access memory (SDRAM) modules and double data rate (DDR) memory modules, with operating speeds in a range from 100 MHz to 800 MHz, may have a multi-drop configuration in which a command/address bus CA is simultaneously coupled to eight or nine DRAM devices.
A memory module 10 may have about 20 command/address pins, 64 (8×8) data pins, about 60 power pins, and a few other pins for specific functions. For example, a memory module with SDRAM devices may have 168 pins. With DDR memory devices, the memory module may have 184 pins. With DDR2 memory devices, the memory module may have 232 pins.
As memory devices evolve, operating speeds supported by the memory devices may increase. In addition, the number of pins may increase. For example, a maximum data transfer rate of a DDR3 memory is about 1,600 Mbps. A next-generation memory developed after the DDR3 memory may have a data transfer rate of about 3,200 Mbps. However, the next generation memory may not stably receive or transmit in noisy environments if using conventional single-ended signaling in which one data bit is received or transmitted using one data pin. Specifically, when memory devices have an operating clock frequency over one GHz, a desired signal integrity (SI) may not be achieved due to capacitive loads of nodes (i.e., nodes coupled to the memory devices).
A next generation memory device may use differential signaling, in which one data bit is received or transmitted using two data pins. Differential signaling may be needed to support a data transfer rate of more than about 3,200 Mbps.
However, a memory module that uses differential signaling requires twice as many pins as those of a memory module that uses single ended signaling because two data pins are required to transmit or receive one bit. For example, when there are 64 data lines, as shown in FIG. 1, 128 data pins are required to transmit or receive 64 data bits. It is currently difficult to design a memory module having more than 250 pins due to current personal computer (PC) design limits and associated mechanical limits. Thus, it is difficult to design the memory module using the differential signaling due to the increase of the number of pins.
When the number of memory devices included in a memory module is reduced so as to avoid the design limits restricting the number of pins in a memory module, data throughput of a memory module decreases.
In addition, in the conventional memory module configuration, the number of pins of a memory module is increased in a circumstance where a first memory module couples to a second memory module via a point-to-point connection so as to reduce the effect of the capacitive loads for the purpose of high-speed operation.
Therefore, it is difficult to use conventional memory modules having conventional command/address bus architecture and the conventional data bus architecture in next generation DRAM having differential signaling and operating at a clock frequency of a few GHz.